منابع مشابه
PTL: PRAM translation layer
In this paper, we attempt to replace NAND Flash memory with PRAM, while PRAM initially targets replacing NOR Flash memory. To achieve it, we need to handle wear-leveling issue of PRAM since the maximum number of writes in PRAM is only 10. Thus, we have proposed PRAM Translation Layer (PTL) to resolve endurance problem for a PRAM-based storage system. We modified FlashSim to support both PRAM an...
متن کاملPTL: A Propositional Typicality Logic
We introduce Propositional Typicality Logic (PTL), a logic for reasoning about typicality. We do so by enriching classical propositional logic with a typicality operator of which the intuition is to capture the most typical (or normal) situations in which a formula holds. The semantics is in terms of ranked models as studied in KLM-style preferential reasoning. This allows us to show that ratio...
متن کاملArea and Timing Models for PTL Macrocells
PTL represents a viable alternative to standard CMOS for the implementation of specific units in performance-constrained systems. Unfortunately, this design style has not found wide acceptance in the designers’ community, due to the lack of an established flow for automatic synthesis. In this paper, we present a procedure for constructing area and timing models for PTL macrocells. This is an ke...
متن کاملSynthesis of PTL-nets with Partially Localised Conflicts
We discuss the problem of constructing PT-nets with localities (PTL-nets) from transition systems with arcs labelled by multisets of transitions (steps). We first outline how this can be done within the existing general solution based on the regions of step transition systems and fixed co-location relations. We then drop the latter assumption and show that this does not really matter when one a...
متن کاملArea Efficient Parallel Multipliers Using Pass Transistor Logic (PTL)
In recent years, total power dissipation and area are one of the most important challenges in VLSI design. By reducing the number of transistors in the circuits and the design structures are may occupied small area and ultra-low power design. In this project based on AND gates and full adders are designed using pass transistor logic (PTL) and different techniques are used for low power in AND G...
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ژورنال
عنوان ژورنال: Logopaedica Lodziensia
سال: 2018
ISSN: 2657-4381,2544-7238
DOI: 10.18778/2544-7238.02.15